FAQ
What is BPU memory Cache?
In this section, we provide the memory functions hbUCPMallocCached and hbUCPMalloc to allocate DDR read/write memory.
In which, the hbUCPMallocCached is used for allocating the cacheable memory space, and the hbUCPMemFlush function is used to flush the cache.
The cache mechanism is determined by the memory architecture of the platform, as shown in the following figure. The cache between CPU and memory is used as a data cache, however, there is no cache between the BPU/DSP/JPU/VPU/PYRAMID/STITCH/GDC backend hardware and main memory. Therefore, the misuse of the cache can cause problems in data reading/writing accuracy and efficiency.
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When the CPU has finished writing data, it needs to actively flush the data in the cache to the memory, otherwise other hardware accessing the same memory space may read the old data from before.
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The CPU also needs to actively INVALIDATE the data in the Cache before accessing it when the other backend hardware has finished writing the data, otherwise the CPU will preferentially read the old data previously cached.
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In the process of continuous model inference, model outputs are recommended to apply for memory with Cache to accelerate the efficiency of repeated CPU reads and writes, while model inputs can apply for non-Cache memory if they do not need to be read by the CPU.
What is the physical/virtual address in BPU memory?
In the J6 processor architecture, all hardware share the DDR memory, and a physically contiguous section of memory can be requested through the
hbUCPMallocCached and hbUCPMalloc interfaces.
The return values of these functions are wrapped in the hbUCPSysMem data structure,
and the phyAddr and virAddr fields correspond to the physical and virtual addresses of its memory space, respectively.
As this memory space is contiguous, both physical and virtual addresses can be represented, read, and written by the first address. However, in practice, it is recommended to use virtual addresses in preference in non-essential scenarios.