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hbUCPBackend

#define HB_UCP_CORE_ANY (0 << 0) #define HB_UCP_BPU_CORE_0 (1ULL << 0) #define HB_UCP_BPU_CORE_1 (1ULL << 1) #define HB_UCP_BPU_CORE_2 (1ULL << 2) #define HB_UCP_BPU_CORE_3 (1ULL << 3) #define HB_UCP_BPU_CORE_ANY (1ULL << 7) #define HB_UCP_DSP_CORE_0 (1ULL << 8) #define HB_UCP_DSP_CORE_1 (1ULL << 9) #define HB_UCP_DSP_CORE_ANY (1ULL << 15) #define HB_UCP_GDC_CORE_0 (1ULL << 16) #define HB_UCP_GDC_CORE_1 (1ULL << 17) #define HB_UCP_GDC_CORE_ANY (1ULL << 19) #define HB_UCP_STITCH_CORE_0 (1ULL << 20) #define HB_UCP_LKOF_CORE_0 (1ULL << 24) #define HB_UCP_JPU_CORE_0 (1ULL << 25) #define HB_UCP_JPU_CORE_1 (1ULL << 26) #define HB_UCP_JPU_CORE_2 (1ULL << 27) #define HB_UCP_JPU_CORE_ANY (1ULL << 29) #define HB_UCP_VPU_CORE_0 (1ULL << 30) #define HB_UCP_PYRAMID_CORE_0 (1ULL << 35) #define HB_UCP_PYRAMID_CORE_1 (1ULL << 36) #define HB_UCP_PYRAMID_CORE_2 (1ULL << 37) #define HB_UCP_PYRAMID_CORE_ANY (1ULL << 38) #define HB_UCP_ISP_CORE_0 (1ULL << 39) #define HB_UCP_ISP_CORE_1 (1ULL << 40) #define HB_UCP_ISP_CORE_ANY (1ULL << 41)

Task execution hardware, can be used in combination, for example: HB_UCP_DSP_CORE_0 | HB_UCP_GDC_CORE_0 represents that the current task can use either the DSP 0 core or the GDC 0 core, the scheduling is leftto the UCP's own decision based on the load.

Attention

HB_UCP_CORE_ANY must be used alone and cannot be ORed with other backends.

  • Member

    Member NameDescription
    HB_UCP_CORE_ANYArbitrary executable hardware on Soc.
    HB_UCP_BPU_CORE_0BPU core 0.
    HB_UCP_BPU_CORE_1BPU core 1.
    HB_UCP_BPU_CORE_2BPU core 2.
    HB_UCP_BPU_CORE_3BPU core 3.
    HB_UCP_BPU_CORE_ANYArbitrary BPU core.
    HB_UCP_DSP_CORE_0DSP core 0.
    HB_UCP_DSP_CORE_1DSP core 1.
    HB_UCP_DSP_CORE_ANYArbitrary DSP core.
    HB_UCP_GDC_CORE_0GDC core 0.
    HB_UCP_GDC_CORE_ANYArbitrary GDC core.
    HB_UCP_STITCH_CORE_0STITCH core 0.
    HB_UCP_LKOF_CORE_0LKOF core 0.
    HB_UCP_JPU_CORE_0JPU core 0.
    HB_UCP_JPU_CORE_1JPU core 1.
    HB_UCP_JPU_CORE_2JPU core 2.
    HB_UCP_JPU_CORE_ANYArbitrary JPU core.
    HB_UCP_VPU_CORE_0VPU core 0.
    HB_UCP_VPU_CORE_ANYArbitrary VPU core.
    HB_UCP_PYRAMID_CORE_0PYRAMID core 0.
    HB_UCP_PYRAMID_CORE_1PYRAMID core 1.
    HB_UCP_PYRAMID_CORE_2PYRAMID core 2.
    HB_UCP_PYRAMID_CORE_ANYArbitrary PYRAMID core.
    HB_UCP_ISP_CORE_0ISP core 0.
    HB_UCP_ISP_CORE_1ISP core 1.
    HB_UCP_ISP_CORE_ANYArbitrary ISP core.